1. Field of the Invention
The present invention relates to the field of comparators in BICMOS technology and, more specifically, to a comparator withstanding a small supply voltage (under 3 volts). The present invention more specifically relates to a comparator which withstands a large input voltage excursion, that is, the input voltages of which can have excursions close to the supply voltage, and which has a large output voltage excursion, that is, the output voltage of which switches between two voltages as close as possible to the supply voltages. This type of comparator is generally called an input and output rail-to-rail comparator.
2. Discussion of the Related Art
FIG. 1 shows a first conventional example of such a comparator. The comparator is formed of a differential stage 1, two positive and negative input terminals 2 and 3 which respectively receive voltages V+ and V- to be compared. Terminals 2 and 3 are purely arbitrarily said to be positive and negative, to define the direction of differential input voltage AV of the comparator. An output terminal 4 of stage 1 controls a switch K (for example, a bipolar transistor) mounted in series with a current source 5 between two terminals A and M on which are respectively applied high and low supply voltages Vdd and Vss.
In the example shown in FIG. 1, stage 1 is formed with two P-channel MOS transistors MP1, MP2, the gates of which are respectively connected to terminals 2 and 3 and the respective sources of which are connected, via a current source 6, to terminal A. The drains of transistors MP1 and MP2 are connected, via an active load 7, to terminal M. Active load 7 is, for example, formed of two NPN-type bipolar transistors T1, T2 mounted as a current mirror and respectively associated, each, with one of MOS transistors MP1, MP2. Transistor T1, associated with transistor MP1, is diode-mounted and the collector of transistor T2, associated with transistor MP2, defines output terminal 4 of differential stage 1. The respective collectors of transistors T1 and T2 are connected to the respective drains of transistors MP1 and MP2, while their emitters are connected to terminal M. Terminal 4 is connected to a control input of switch K (for example, the base of an NPN-type bipolar transistor). The midpoint of the series association of current source 5 and of switch K forms an output terminal S of the comparator.
When voltage V+ is smaller than voltage V-, voltage difference .DELTA.V between terminals 2 and 3 is negative and current I1 through transistor MP1 is greater than current I2 through transistor MP2. Since transistor T2 attempts copying current I1, it saturates and prevents a control current from flowing to switch K which is thus open. Output voltage Vs of the comparator then corresponds to voltage Vdd-Vss, minus the voltage drop in current source 5. This voltage drop corresponds, for example if the current sources are made by means of bipolar transistors, to the collector-emitter voltage drop of a saturating bipolar transistor. If the current sources are formed of MOS transistors, this voltage drop corresponds to a drain-source voltage drop. Current sources 5 and 6 are generally formed of transistors mounted as a current mirror.
When V+=V-(DV=0), currents I1 and I2 are balanced and switch K is open. Terminal S then is substantially at potential Vdd.
When voltage V+ is greater than voltage V-(DV&gt;0), current I2 is greater than current I1. The current mirror between transistors T1 and T2 maintains the collector currents of transistors T1 and T2 identical. As a result, the current excess of transistor MP2 with respect to transistor MP1 flows towards the control terminal of switch K (the base of a bipolar transistor) which closes. Terminal S then is at voltage Vss plus the voltage drop in switch K in the closed state (the collector-emitter voltage drop of the saturating bipolar transistor). Thus, the output voltage excursion substantially corresponds to the supply voltage.
However, for such an assembly to operate, input voltages V+ and V- have to fulfil a common mode constraint, that is, a constraint on the mean voltage level between voltages V+ and V- (independently from differential voltage V). If the voltage of one of terminals 2, 3 is greater than potential Vdd, minus a threshold voltage Vth corresponding to the threshold (gate-source) voltage of transistor MP1 or MP2 plus voltage drop V6 in current source 6, the comparator no longer operates properly. If V-&gt;Vdd-Vth, transistor MP2 is blocked and switch K cannot receive any current on its control terminal. Terminal S thus is substantially at potential Vdd, whatever voltage V+. If V+&gt;Vdd-Vth, transistor MP1 is blocked and current I1 is null. Transistors T1 and T2 thus are both off (they receive no base current).
In practice, the comparator of FIG. 1 thus requires a common mode input voltage smaller by approximately 1 to 1.5 volts than the positive supply voltage. In other words, the voltages of terminals 2 and 3 have to be both smaller by approximately 1 to 1.5 volts than voltage Vdd for the comparator to operate properly.
A conventional assembly such as illustrated in FIG. 1 has the advantage of being able to operate under very small supply voltages (typically, on the order of 2 volts). However, it does not enable having input voltages which, in common mode, can extend over the entire supply voltage range.
FIG. 2 shows a second example of a conventional comparator which can operate under a small supply voltage. The assembly of FIG. 2 is similar to that of FIG. 1, but inverted with respect to terminals A and M and using N-channel MOS transistors instead of the P-channel MOS transistors of FIG. 1 and PNP-type bipolar transistors instead of the NPN-type bipolar transistors of FIG. 1. The elements of FIG. 2 which are identical to those in FIG. 1 have been referred to by the same references. Those having the same function, but which differ by their type (NPN instead of PNP) or channel (N instead of P) have been designated with the same references associated with an apostrophe (').
The assembly of FIG. 2 suffers from the same limitations as that in FIG. 1, but with respect to low supply voltage Vss. Indeed, the operation of differential input stage 1' is limited to input voltages which are, in common mode, greater than low supply voltage Vss, plus a threshold voltage Vth'. Threshold voltage Vth' here corresponds to the threshold (gate-source) voltage of an N-channel MOS transistor, plus voltage drop V6' in current source 6'.
In the voltage operating range of the comparator of FIG. 2, if .DELTA.V.sup.3 0, switch K' (for example, a bipolar PNP-type transistor) is open and Vs&gt;&gt;Vss. If .DELTA.V&lt;0, switch K' is closed (the bipolar transistor forming it saturates) and Vs.apprxeq.Vdd.
However, if V-&lt;Vss+Vth', transistor MN2 is blocked whatever the value of voltage V+ and thus cannot draw current from the base of the transistor constitutive of switch K' which is thus open. Voltage Vs then is low, independently from potential difference .DELTA.V. If V+&lt;Vss+Vth', transistor MN1 is blocked independently from differential voltage DV. Transistors T'1 and T'2 are then blocked.
In practice, the comparator of FIG. 2 thus requires input voltages which are both greater by approximately 1 to 1.5 volts than the negative supply voltage, and thus a common mode voltage respecting this constraint.
It would be desirable to have a comparator withstanding a common mode voltage at least over the entire supply voltage range (Vdd-Vss) while maintaining a large output voltage excursion and a possibility of supply at very small voltage (on the order of 2 volts).